Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 889

Table A-32. External Port DMA Register Bit Descriptions (RW) (Cont'd)
Bit Name
25 (RO) DIRS
31–26 Reserved
Peripheral Registers
The registers in the following sections are used for the peripherals that are
not routed through the signal routing units (SRU, SRU2).
Link Port Registers
The following sections describe the link port status and control registers.
Control Register (LCTLx)
Figure A-28 and
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Description
DMA Transfer Direction Status.
0 = DMA direction is external reads
1 = DMA direction is external writes
This is useful for delay line DMA where the transfer direction
changes with the state of the DMA state machine.
For standard DMA, DIRS reflects the state of the TRAN bit.
Table A-33 describe the bit fields within this register.
Registers Reference
A-63