Interrupt Versus Channel Priorities - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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interrupt-driven I/O under control of the processor core. Refer to the spe-

cific peripheral chapter for more information.

Interrupt Versus Channel Priorities

At their default setting shown in

do not match the DMA channel priorities. However, if both priorities

schemes should match, the DMA interrupt priorities can be re-assigned by

dedicated settings of the

Table 2-29. Default Channel vs. Interrupt Priorities

Programmable

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Default Interrupt

ADSP-214xx SHARC Processor Hardware Reference

2-29, the DMA interrupt priorities

DMA Channel Priority

SPORT5–0, 12 channels

IDP7–0, 7 channels

SPI – 1 channel

MLB – 31 channels

SPI B – 1 channel

MTM (WR/RD) – 2 channels

UART0(Tx/Rx) – 2 channels

SPORT7–6, 4 channels

Accelerator (In/Out) 2 channels

EPDMA1–0, 2 channels

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