Debug Features; Shadow Register - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

LSRs are gated by mask bits and then ORed together to generate the link
service request interrupt. The
the receive (
LRRQ_MSK
When the mask bit is set, the interrupt is allowed to pass into the inter-
rupt priority encoder. The maximum latency between asserting the
or signals and latching an interrupt is 2 to 3
LACK
The interrupt routine must read the
link port to service and whether it is a transmit or receive request. The
link service request status of the port is set whenever the port is not enable
and one of
LxACK
If link service requests are in use, they should be masked out when the
assigned link buffers are being enabled, disabled, or when the link port is
being unassigned in
may be generated.

To avoid the possibility of spurious interrupts, programs can mask
the LSRQ interrupts and poll the appropriate request status bits
until it is cleared and then unmask the interrupt.

Debug Features

The following sections provide information on features that help in
debugging link port software.

Shadow Register

The shadow status register can be read without clearing the interrupt bits.
For more information, see "Link Port Registers" on page A-63.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
interrupt requests may be masked by
LSRQ
) or transmit (
LTRQ_MSK
or is asserted high.
LxCLK
register. Otherwise, spurious service requests
LCTLx
Link Ports—ADSP-2146x
) bits of the
cycles.
PCLK
register to determine which
LSTATx
register.
LCTLx
LCLK
4-21