Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 191

31
Unused
Figure 3-14. Core Address Mapping to Row, Column Addresses (Page)
One advantage of the page interleaving is that the effective page size is up
to four pages (assuming four banks activated) and all the addresses are
sequential. If using delay line DMA mode, the addresses for a long delay
line are all sequential, simplifying the addressing. Moreover, DDR2
sequential addressing provides maximum performance.
Bank Interleaving Map
Programming the
scheme. In this scheme consecutive pages sit in the same bank. The bank
address bits follow most significant row address bits. This is shown in
Figure 3-15.
31
Bank
Unused
Address
Figure 3-15. Core Address Mapping to Row, Column Addresses (Bank)
One advantage of bank interleaving is that the effective page size is also up
to four pages (assuming four banks activated) but the addresses of the four
pages are not sequential. If the program uses two external port DMAs
pointing to the DDR2 space, this scheme has advantages since every bank
has its one DMA buffer addressing.
Address Width Settings
Number Internal Banks (DDR2BC). The controller assumes the DDR2
is comprised of eight bank devices. However, DDR2 can use four bank
devices by not connecting the
ADSP-214xx SHARC Processor Hardware Reference
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Row Address
bit to 1 selects the bank interleaving
DDR2ADDRMODE
Row Address
ADDR18
Bank
Column Address
Address
Column Address
pin and programming the
External Port
0
0
DDR2BC
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