Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 636

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Data Transfers

discarded, and the

2. If core access to a SPI master is unable to keep up with the trans-

mit/receive stream during a transfer operation (because of an

interrupt or another reason) the SPI stalls the

data is read/written into the

data stream.

DMA Buffer Status

If the DMA engine is unable to keep up with the transmit/receive stream

during a transfer operation because of latency caused by using multiple

DMA channels, the SPI operates according to the states of the

bits in the SPICTLx register.

transmits zeros on the

new transfer initiate command.

transmits the last word transmitted before the transmit buffer

became empty.

= 1 and the receive buffer is full, the device continues to

receive new data from the

= 0 and the receive buffer is full, the incoming data is dis-

carded, and the

Core Transfers

bit defines when the receive buffer can be read. The

defines when the transmit buffer can be filled. The end of a single word

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= 0 and the receive buffer is full, the incoming data is

condition bits are set indicating an exception in the

= 1 and the transmit buffer is empty, the device repeatedly

= 0 and the transmit buffer is empty, the device repeatedly

ADSP-214xx SHARC Processor Hardware Reference

buffers. In this scenario

pin. One word is transmitted for each

pin, overwriting the older data in

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