Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 626

Functional Description
However, the
SPICLK
the period. For a slave with
SPICLK
as the
SPI_DS_I
For = 1, a transfer starts with the first active edge of
CPHASE
both slave and master devices. For a master device, a transfer is considered
complete after it sends and simultaneously receives the last data bit. A
transfer for a slave device is complete after the last sampling edge of
.
SPICLK
Single Master Systems
Figure 15-2 illustrates how the SHARC processor can be used as the slave
SPI device. The 16-bit host (A Blackfin ADSP-BF53x processor) is the
SPI master. The processor can be booted via its SPI interface to allow
application code and data to be downloaded prior to runtime.
B
ADSP-BF537
SCLK
SPISSEL
MOSI
MISO
Figure 15-2. SHARC Processor as SPI Slave
Figure 15-3 shows an example SPI interface where the SHARC processor
is the SPI master. With the SPI interface, the processor can be directed to
alter the conversion resources, mute the sound, modify the volume, and
power down the AD1855 stereo DAC.
15-10
www.BDTIC.com/ADI
starts toggling after a delay equal to one-half (0.5)
input transitions to low.
DPI (SPI_CLK_I)
DPI (SPI_DS_I)
DPI (SPI_MOSI_I)
DPI (SPI_MISO_O)
SLAVE SPI DEVICE
ADSP-214xx SHARC Processor Hardware Reference
= 0, the transfer starts as soon
CPHASE
S
ADSP-214xx
for
SPICLK