Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 759

Table 21-5. Slave Mode Setup Interaction (Slave Addressed as Receiver)
TWI Controller Master
Interrupt: TWISINIT – Slave transfer has been
initiated.
Interrupt: TWIRXS – Receive buffer has 1 or 2
bytes (according to TWIRXINT).
...
Interrupt: TWISCOMP – Slave transfer com-
plete.
Master Mode Clock Setup
Master mode operation is set up and executed on a per-transfer basis. An
example of programming steps for a receive and for a transmit are given
separately in following sections. The clock setup programming step listed
here is common to both transfer types.
Program the
TWIDIV
clock low duration.
Master Mode Transmit
Follow these programming steps for a single master mode transmit:
1. Program the
ted during the address phase of the transfer.
2. Program the
transmitted. It is considered an error to complete the address phase
of the transfer and not have data available in the transmit FIFO
buffer.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Two Wire Interface Controller
Processor
Change on the next sides always.
Interrupt Acknowledge: W1C the TWIIRPTL
register.
Read receive FIFO buffer.
Change on the next sides always.
Interrupt Acknowledge: W1C the TWIIRPTL
register
...
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
register. This defines the clock high duration and
register. This defines the address transmit-
TWIMADDR
or
TXTWI8 TXTWI16
registers. This is the initial data
21-21