Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 499

Receive Buffers (RXSPxA/B)
The receive buffers (
fers SPORT7–0 respectively. These 32-bit buffers become active when the
SPORT is configured to receive data on the A and B channels. When a
SPORT is configured as a receiver, the
automatically loaded from the receive shifter when a complete word has
been received. The data is then loaded to internal memory by the DMA
controller or read directly by the program running on the processor core.
Buffer Status
Serial ports provide status information about data buffers via the
and status bits and error status via
DXS_B
Depending on the
or
TXSPxy RXSPxy
If your program causes the core processor to attempt to read from an
empty receive buffer or to write to a full transmit buffer, the access is
delayed until the buffer is accessed by the external I/O device. This delay
is called a core processor hang. If you do not know if the core processor
can access the receive or transmit buffer without a hang, the buffer's status
should be read first (in
The status bits in
core processor even when the serial port is disabled. Disable the serial port
when writing to the receive buffer or reading from the transmit buffer.
Two complete 32-bit words can be stored in the receive buffer while a
third word is being shifted in. The third word overwrites the second if the
first word has not been read out (by the processor core or the DMA con-
troller). When this happens, the receive overflow status bit is set in the
serial port control register. Almost three complete words can be received
without the receive buffer being read before an overflow occurs. The over-
flow status is generated on the last bit of the third word. The
bits are sticky and are cleared only by disabling the serial port.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
,
RXSP7–0A RXSP7–0B
setting, these bits reflect the status of either the
SPTRAN
data buffers.
) to determine if the access can be made.
SPCTLx
are updated during reads and writes from the
SPCTLx
) are the 32-bit receive data buf-
and
RXSPxA RXSPxB
bits in the
DERR_x
Serial Ports
registers are
DXS_A
register.
SPCTL
status
DERR_x
10-41