Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 720

Functional Description
the RS-485 data interface standard. The UART has its own set of control
and status registers
UARTx_RX_I
RX
SR
RX CONTROL
GENERATOR
TX CONTROL
UARTx_TX_O
TX
SR
Figure 20-1. UART Functional Block Diagram
The UART is a DMA-capable peripheral with support for separate trans-
mit and receive DMA master channels. It can be used in either DMA or
core modes of operation. The core mode requires software management of
the data flow using either interrupts or polling. The DMA method
requires minimal software intervention as the DMA engine itself moves
the data. For more information, see "DMA Transfers" on page 20-13.
Either one of the peripheral timers can be used to provide a hard-
ware-assisted autobaud detection mechanism for use with the UART. See
the "Autobaud Detection" on page
20-6
www.BDTIC.com/ADI
(Figure 20-1).
RX
RBR
BAUD
TX
RBR
ADSP-214xx SHARC Processor Hardware Reference
LINE CONTROL/
STATUS
DIVISOR
LATCH
LINE CONTROL/
STATUS
CORE INTERFACE
20-21.
MASTER
RX
DMA
UART DMA
ARBITER/DATA MUX
MASTER
TX
DMA
CORE
BUS
IOD0
BUS