Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 516

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Programming Model
become non-empty by polling the
operation, initialize the transmit buffer with the first data word to
be transmitted.
7. Configure and enable multichannel in the multichannel control
registers (
Multichannel Mode Backward Compatibility
In previous SHARC models, the serial port pair used the same control reg-
ister (
) to program multichannel mode. In the ADSP-214xx
SPMCTL01
processors, this register is simply renamed to
has been added. Note that both however are identical. Programs
SPMCTL1
using the older code simply need to change from the
the
register or the
SPMCTL0
The following steps should be taken to port the code to the ADSP-214xx
products.
1. Instead of programming
.
SPMCTLy
2. In previous processors the data direction bit in the
was hard coded in multichannel mode (where the even port is
always the transmitter and the odd port is always the receiver). But
in the ADSP-214xx processors, the direction (
ored and therefore should be set as required.
3. Routing models for hard coded multichannel pairs used the even
SPORT for the clock and the odd SPORT for the frame sync. The
signal was derived from the even frame sync. In the
TDV
ADSP-214xx processors, these limitations no longer apply. All
SPORTs operate completely independently. Therefore every
SPORT requires the clock and frame sync to be routed. The
signal is separate and is fed into the SRU unit.
10-58
www.BDTIC.com/ADI
and
SPMCTLx
SPMCTLy
SPMCTL1
SPMCTLxy
ADSP-214xx SHARC Processor Hardware Reference
/
bits. For core mode
DXS0_A
B
).
and a new register,
SPMCTL0
SPMCTL01
register.
only, program both
SPTRAN
register to
and
SPMCTLx
register
SPCTL
bit) is hon-
TDV

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