Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

The PWM sync enable feature allows programs to enable the
bits to independently start the main counter without
PWN_SYNC_ENx
enabling the corresponding PWM module using the
chronize different groups, enable the corresponding group's
the same time. In order to stop the counter both the
PWM_SYNC_DISx

Interrupts

The following sections provide information on the PWM and interrupt
generation. Table 7-5
Table 7-5. PWM Interrupt Overview
Interrupt Source
PWM (Edge/center
aligned, single/double
update, 4 channels)
Typically the PWM interrupt is used to periodically execute an interrupt
service routine (ISR) to update the two PWM channel duties according to
a control algorithm based on expected system operation. The PWM inter-
rupt can trigger the ADC to sample data for use during the ISR. During
processor boot the PWM is initialized and program flow enters a wait
loop. When a PWM interrupt occurs, the ADC samples data, the data is
algorithmically interpreted, and new PWM channel duties are calculated
and written to the PWM. More sophisticated implementations include
different startup, runtime, and shutdown algorithms to determine PWM
channel duties based on expected behavior and further features.
During initialization, the
period and the
pulse widths. The PWM interrupt is assigned to one of the core's User
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bits should be set in this register.
provides an overview of PWM interrupts.
Interrupt Interrupt
Condition Completion
Period start
register is written to define the PWM
PWMTM
registers are written to define the initial channel
PWMCHx
Pulse Width Modulation
PWM_ENx
PWM_ENx
PWM_DISx
Interrupt Acknowledge
W1C (Write 1-to-clear)
PWMGSTAT + RTI
instruction
bits. To syn-
bit at
and
Default IVT
Need to route
PWMI (PICRx)
to any PxxI
7-25