Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 505

DMA Chaining
Each channel also has a DMA chaining enable bit (
in its control register.
SPCTLx
Each SPORT DMA channel also has a chain pointer register (
The register functions are used in chained DMA operations.
CPSPxy
In chained DMA operations, the processor's DMA controller automati-
cally sets up another DMA transfer when the contents of the current
buffer have been transmitted (or received). The chain pointer register
( ) functions as a pointer to the next set of buffer parameters stored
CPSPxy
in external or internal memory. The DMA controller automatically down-
loads these buffer parameters to set up the next DMA sequence. For more
information on SPORT DMA chaining, see
page 2-32.
DMA chaining occurs independently for the transmit and receive channels
of each serial port. Each SPORT DMA channel has a chaining enable bit
( or
SCHEN_A SCHEN_B
when cleared (= 0), disables DMA chaining. Writing all zeros to the
address field of the chain pointer register (

The chain pointer register should be cleared first before chaining is
enabled.
The I/O processor responds by auto-initializing the first DMA parameter
registers with the values from the first TCB, and then starts the first data
transfer.

Although the word lengths can be 3 to 32 bits, transmitting or
receiving words smaller than 7 bits at the full clock rate of the serial
port may cause incorrect operation when DMA chaining is
enabled. Chaining locks the processor's internal I/O bus for several
cycles while the new transfer control block (TCB) parameters are
being loaded. Receive data may be lost (for example, overwritten)
during this period.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
) that when set (= 1), enables DMA chaining and
Serial Ports
and
SCHEN_A
"DMA Chaining" on
) also disables chaining.
CPSPxy
)
SCHEN_B
).
CPSPxy
10-47