Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 662

Functional Description
pins through the signal routing unit (SRU). The timer signal functions as
an output signal in PWM_OUT mode and as an input signal in
WDTH_CAP and EXT_CLK modes. To provide these functions, each
timer has four, 32-bit registers shown in
Figure 16-1. Timer Block Diagram
The registers for each timer are:
• Timer x control (
• Timer x word count (
• Timer x word period (
• Timer x word pulse width (
The timers also share a common status and control register—the timer
global status and control (
16-6
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PMD/DMD BUS
32
PERIOD BUFFER
(32 BIT)
32
32
TIMERx_PERIOD
(32 BIT)
TIMERx_COUNTER
(32 BIT)
EQUAL?
CONTROL CONTROL
LOGIC
32
(READ ONLY)
) register
TMxCTL
) register
TMxCNT
TMxPRD
TMxW
) register.
TMSTAT
ADSP-214xx SHARC Processor Hardware Reference
Figure 16-1.
32
WIDTH BUFFER
(32 BIT)
32
TIMERx_WIDTH
(32 BIT)
EXPIRE
EQUAL?
LOGIC
) register
) register