Fft Accelerator - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

FFT Accelerator

The FFT accelerator (shown in
floating-point FFT. The accelerator's data and twiddle coefficient inter-
face is designed to connect to the processor's DMA engine (acting like a
peripheral) and implements a synchronous pipeline read/write protocol
with a pipeline depth of 1.
FFT CONTROL
REGISTERS
256x2
C
O
E
F
F
I
C
I
E
N
T
S
Figure 6-1. FFT Block Diagram
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
FFT/FIR/IIR Hardware Modules
Figure
CORE PMD/DMD
BUS
FFT CONTROLLER
INPUT
BUFFER
FFT
COEFF
COMPUTE
ACCESS
UNIT
CONTROL
(Complex
Butterfly)
6-1) implements radix-2 complex
IOD0
BUS
DMA
CONTROLLER
DATA
ACCESS
CONTROL
OUTPUT
BUFFER
256x4
D
A
T
A
6-3