Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 773

PLL Start-Up
Before the PLL can start settling, the
several micro-seconds under the following conditions. For PLL informa-
tion, see the appropriate product data sheet.
• Valid and stable core voltage (
• Valid and stable I/O voltage (
• Valid and stable clock input (
The chip reset circuit is shown in
lock to the
CLKIN
process. A delayed core reset signal (
counter after
RESET
μs for minimum
PLL is triggered for settling after reset is deasserted.
RESET
CLKIN
Figure 22-2. Chip Reset Circuit
After the external processor
tling. The rest of the chip is held in reset for 4096
is deasserted by an internal reset signal.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Figure
frequency before the core can execute or begin the boot
is transitioned from low to high (approximately 400
). The delay circuit is activated at the same time the
CLKIN
Core Reset Delay Circuit
ENA_CNT
CORE_RST
CLKIN
12-bit Counter
Count 4096 CLKIN Cycles
signal is deasserted, the PLL starts set-
RESET
Power Management
signal should be asserted for
RESET
)
VDDINT
and
VDDEXT VDD_DDR2
)
CLKIN
22-2. The PLL needs time to
) is triggered by a 12-bit
RESETOUT
PLL_RESET
CLKIN
PLL
Delayed Internal
Core Processor Reset
RESETOUT
CLKIN
)
cycles after
RESET
22-9