Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 901

General Control Register (FFTCTL1)
The global control register (
in Table A-41 is used to enable, start, and reset the FFT module. It is also
used to enable DMA and debug operation.
31 30
15 14 13
FFT_DBG
Debug Mode Enable
FFT_DMAEN
DMA Enable
Figure A-33. FFTCTL1 Register
Table A-42. FFTCTL1 Register Bit Descriptions (RW)
Bits
0
1
2
3
5–4
ADSP-214xx SHARC Processor Hardware Reference
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FFTCTL1
29 28 27 26 25 24 23 22
12 11 10 9 8 7 6
Name Description
FFT_RST Reset Accelerator. Setting this bit puts the accelerator
into reset mode. Explicit clearing of this bit is necessary
to take the accelerator out of reset.
0 = Normal operation
1 = Reset
FFT_EN Accelerator Enable.
0 = Disable
1 = Enable
FFT_START Start Accelerator.
0 = Idle
1 = Start
FFT_DMAEN DMA Enable.
0 = Disable
1 = Enable
Reserved
Registers Reference
) shown in Figure A-33
21 20 19 18 17 16
5 4 3 2 1 0
FFT_RST
Accelerator Reset
FFT_EN
Accelerator Enable
FFT_START
Accelerator Start
and described
A-75