Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 250

Effect Latency
Table 3-33 illustrates the performance of code execution depending on
different access types.
Table 3-33. Core Throughput
Access
Sequential uninter-
rupted reads
Non sequential uninter-
rupted reads
* In this case SDC has to fetch 3 data (16-bit) for each instruction.
First 48-bit instruction of a sequential read will take 8 cycles for CL = 2 and 9 cycles for
CL = 3, thereafter it is two instructions per 6 cycles.
The instruction available cycles will look like - 8, 10, 14, 16, 20, 22, 26, 28 ... (CL = 2)
When executing from external asynchronous memory, instruction
throughput depends on the settings of asynchronous memory such as the
number of wait states, the ratio of core to peripheral clock and other
settings. For details, please refer to the external port global control register
( ), the
EPCTL AMICTLx
ADSP-2148x External Port Registers" on page
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific). After the
AMI/SDRAM/DDR2 registers are configured the effect latency is 1.5
cycles minimum and 2
PCLK
After the external port register is configured the effect latency is 4
cycles. This is the valid for the worst case of core to SDRAM/DDR2 clock
ratio of 1:4
3-120
www.BDTIC.com/ADI
Data Page Throughput per
Width SDCLK (CL = 2)
16 Same 2 instructions per 6
cycles*
16 Same 1 instructions per 9
cycles
register, and the
SDCTL0
cycles maximum.
PCLK
ADSP-214xx SHARC Processor Hardware Reference
Throughput per
SDCLK (CL = 3)
2 instructions per 6
cycles*
1 instructions per 10
cycles
register in "ADSP-2147x,
A-45.
PCLK