Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 611

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(FS IN , 44.1 kHz)

Figure 14-6. PCG Setup for I2S or Left-Justified DAI

The combined PCGs can provide a selection of synchronous clock fre-

quencies to support alternate sample rates for the ASRCs and external

DACs. However, the range of choices is limited by

audio left-justified, I

Many DACs also support 384, 512, and 786x FS for

allows some additional flexibility in choosing

Note the falling edge of

of FS. This requires that the phase of the

mon PCG (PCG A) be adjustable.

While the frequency of the master DAC clock (

chronous with the sample rate supplied to the external DAC, there is no

fixed phase requirement.

ADSP-214xx SHARC Processor Hardware Reference

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FSYNC A (FS OUT )

SCLK A (64 FS OUT )

SCLKB (256 FS OUT )

which is normally fixed at 256:64:1 to support digital

S and right-justified interface modes.

must always be synchronous with both edges

Precision Clock Generator

FS OUT = 65.1 kHz

and FS signals for a com-

LEFT-JUSTIFIED

and the ratio of

) must be syn-

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