Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 631

CLOCK CYCLE#
SPI_CLK_O
CLKPL=0
(SPI MODE 0)
SPI_CLK_O
CLKPL=1
(SPI MODE 2)
SPI_MOSI_O
*
FROM MASTER
SPI_MISO_I
MSB
FROM SLAVE
SPI_FLG_I
FROM MASTER
Figure 15-5. SPI Transfer Protocol for CPHASE = 0
Figure 15-6 shows the SPI transfer protocol for
starts toggling at the beginning of the data transfer where the bit
SPICLK
settings are = 0, and
WL
Slave Select Outputs
If the SPI is enabled and configured as a master, any of the 14 DPI I/O
pins may be used as slave-select outputs. For each
the register, the corresponding
SPIFLG
slave-select output.
For example, if
the chip-level,
SPI_FLG1_O
through SRU programming. For those
corresponding
SPIx_FLGx_PBEN_O
The behavior of the
configuration bit. If
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
1 2 3
MSB 6 5
6 5
= 1.
MSBF
= 1 is set,
DS1EN SPI_FLG1_O
can be connected to any of the DPI pins
is driven low.
output depends on the value of the
SPI_FLGx
= 1, all selected outputs may either remain
CPHASE
Serial Peripheral Interface Ports
4 5 6
3 2
4
4 3 2
CPHASE
DSxEN
is configured as a
SPI_FLGx_O
is driven as a slave-select. At
bits which are not set, the
DSxEN
7 8
1 LSB *
1 LSB *
* = UNDEFINED
= 1. Note that
bit which is set in
CPHASE
15-15