Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 934

Peripheral Registers
Channel Status Configuration Registers
(MLB_CSCRx)
This register, shown in
the status of the current and previous buffer for the given logical channel.
For all bits a 1 means the condition exists.
31 30
BM
Channel x Buffer Empty
BF
Channel x Buffer Full
15 14
STS (11)
Reserved (I/O)
Previous Buffer Start (DMA)
STS (10)
Reserved (I/O)
Previous Buffer Done (DMA)
STS (9)
Receive Packet Start (I/O)
Previous Buffer Detect Break (DMA)
STS (8)
Transmit Service Request (I/O)
Receive Packet Abort (DMA)
STS (6)
Lost Frame Sync
Figure A-50. MLB_CECRx Register
A-108
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Figure A-50
29 28 27 26 25 24 23 22
13 12 11 10 9 8 7 6
ADSP-214xx SHARC Processor Hardware Reference
and described in Table
21 20 19 18 17 16
RDY
Next Buffer Ready
GIRB
Generate Break
5 4 3 2 1 0
STS (0)
Current Buffer Protocol Error
STS (1)
Current Buffer Detect Break
STS (2)
Receive Service Request (I/O)
Current Buffer Done (DMA)
STS (3)
Transmit Service Request (I/O)
Current Buffer Start (DMA)
STS (4)
Buffer Error
STS (5)
Host Bus Error
A-68, shows