Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 134

Register Overview
External Port Control Register (EPCTL). This register enables the exter-
nal banks for the SDRAM or the AMI. Moreover controls accesses
between the processor core and DMA, and between different DMA
channels.
Power Management Control Register (PMCTL). Controls the SDCLK
to core clock ratio related to the AMI or SDRAM timing.
SDRAM Control Register (SDCTL). Configures various aspects of
SDRAM operation. These are control clock operation, bank configura-
tion, and SDRAM commands. Programmable parameters associated with
the SDRAM access timing.
SDRAM Control Status Registers (SDSTATx). Provides information on
the state of the SDC. This information can be used to determine when it
is safe to alter SDRAM control parameters or as a debug aid.
SDRAM Refresh Rate Control Register (SDRRC). Provides a flexible
mechanism for specifying auto-refresh timing.
DDR2CTL0 register contains the bits that control the DDR2 size,
enables mode register and allows forcing of specific DDR2 commands.
DDR2CTL1 register includes the timing programmable parameters asso-
ciated with the DDR2 access timing. All the values for this register are
defined in terms of number of clock cycles from the DDR2 data sheet.
DDR2CTL2 register includes the programmable parameters associated to
the burst type, burst length and CAS latency.
DDR2CTL5–3 registers include the programmable parameters associated
with the DDR2 extended mode registers 1 through 3.
DDR2 Status Registers (DDR2STAT1-0). These registers provide infor-
mation on the state of the DDR controller. This information can be used
to determine when it is safe to alter DDR control parameters or as a debug
aid.
3-4
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ADSP-214xx SHARC Processor Hardware Reference