Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 885

SDMODIFY(20–17)
Used for Predictive Addressing
15
Figure A-26. SDRRC Register
Table A-31. SDRRC Register Bit Descriptions (RW)
Bit
11–0
15–12
16
20–17
31–21
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31 30 29 28 27 26 25 24
14 13 12 11 10 9 8
Name Description
RDIV Refresh Divider Count. This 12-bit field defines the
number of SDCLK cycles between to successive
auto-refresh commands.
Note that RDIV=0 setting is illegal.
Reserved
SDROPT SDRAM Read Optimization. If set (=1) enables read
optimization to improve read throughput for core or
external port DMA access.
0 = Disabled
1 = Enabled
Default setting is 1.
SDMODIFY SDRAM Read Modifier. According to SDROPT bit this
bit should be set to match the DAG or DMA modifier.
0000 = 0
1111 = 15
Default setting is 1.
Reserved
Registers Reference
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
SDROPT
SDRAM Optimization
RDIV (11–0)
Refresh Divider Count
A-59