Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 235

Bit 20 ( ) bit of the external port chain pointer register (
CPDR
changes the data flow direction. If
memory are performed, if
formed. This works similar to the
( ) in the
CHEN DMACx
Listing 3-7. Changing DMA Direction
.section/pm seg_dmda;
/* EP TCB storage order CP-EM-EI-C-IM-II
.var TCB1[6] = 0 , M , extbuffer , N , M , buffer;
.var TCB2[6] = 0 , M , extbuffer , N , M , buffer;
.section/pm seg_pmco;
R0=0;
dm(CPEP0)=R0;
r0 = DEN|CHEN|OFCEN;
dm(DMAC0)=r0;
R2=(TCB1+5) & 0x7FFFF;
R2=bset R2 by 19;
dm(TCB2)=R2;
R2=(TCB2+5) & 0x7FFFF;
R2=bset R2 by 19;
R2=bset R2 by 20;
dm(TCB1)=R2;
dm(CPEP0)=R2;
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
CPDR
is set (=1), internal memory reads are per-
CPDR
bit (bit 19). Bit 8 (
PCI
register must be set (=1) to enable this functionality.
/* clear CPx register */
/* enable DMA channel */
/* load IIx address of next TCB and
mask address */
/* set PCI bit */
/* write address to CPx location of
current TCB */
/* load IIx address of next TCB and
mask address*/
/* clear PCI bit */
/* set CPDR bit */
/* write address to CPx location of
current TCB */
/* write IIx address of TCB1 to CPx
register to start chaining*/
External Port
is cleared (=0) writes to internal
OFCEN
*/
)
CPEPx
) and bit 2
3-105