Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 790

Processor Booting
Boot Mechanisms
In order to ensure proper device booting, the following hardware mecha-
nisms are available on the processor.
• Peripheral boot configuration pins (
peripheral boot stream is activated after power-up.
• Peripheral control and DMA parameter settings define the DMA
channel which is started after
boot configuration pins.
• Peripheral interrupt is enabled after reset for the boot peripheral.
• During kernel load the core is put in IDLE. After the interrupt is
generated the core jumps to reset location and starts kernel
execution.
External Port Booting
The ADSP-214xx processors allow booting through the external port. The
boot setting is configured through the
The asynchronous memory interface (AMI) supports an 8-bit user boot
called AMI boot. Only the
booting. Table 23-2
described in detail in
After
RESETOUT
•
ADDR23–0
• Chip select
• strobe with 23
AMI_RD
• Read input data 7–0
23-8
www.BDTIC.com/ADI
signal is used for AMI (FLASH/EEPROM)
MS1
shows the bit settings for AMI boot. These bits are
"AMI Control Registers (AMICTLx)" on page
deasserted, the processor starts to drive:
to the EPROM/FLASH
MS1
SDCLK
ADSP-214xx SHARC Processor Hardware Reference
) configure which
BOOT_CFGx
is asserted based on the
RESETOUT
pins.
BOOTCFG2–0
cycle wait states
A-21.