Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 987

Table A-85. SPCTLx Register Bit Descriptions (I
Left-Justified) (RW) (Cont'd)
Bit Name
26 DERR_B
(RO)
28–27 DXS_B
(RO)
29 DERR_A
(RO)
31–30 DXS_A
(RO)
ADSP-214xx SHARC Processor Hardware Reference
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Description
Channel B Error Status. SPORT configured as a transmitter, this bit
provides transmit underflow status. As a transmitter, DERR_x bit indi-
cates whether the SPORTx_FS signal (from an internal or external
source) occurred while the DXS_x buffer was empty. The SPORTs
transmit data whenever they detect a SPORTx_FS signal.
0 = No SPORTx_FS signal occurred while TXSPxA/B buffer is empty.
1 = SPORTx_FS signal occurred while TXSPxA/B buffer is empty.
SPORT configured as a receiver, these bits provide receive overflow sta-
tus. As a receiver, DERR_x bit indicates whether the SPORTx_FS sig-
nal (from an internal or external source) occurred while the DXS_x
buffer was full. The SPORTs receive data whenever they detect a
SPORTx_FS signal. As a receiver, it indicates when the channel has
received new data while the receive buffer is full. New data overwrites
existing data.
0 = No SPORTx_FS signal occurred while RXSPxA/B buffer is full.
1 = SPORTx_FS signal occurred while RXSPxA/B buffer is full.
Channel B Data Buffer Status. Indicates the status of the SPORT's
channel B data buffer (RXSPxB or TXSPxB) as follows:
00 = Empty
10 = Partially full
11 = Full
Channel A Error Status. Refer to DERR_B.
Channel A Data Buffer Status. Refer to DXS_B.
Registers Reference
2
S,
A-161