Service Request Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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If the DMA is disabled but the associated link buffer is enabled, then a

maskable interrupt is generated whenever a receive buffer is not empty or

when a transmit buffer is not full. This interrupt is the same interrupt vec-

tor associated with the completion of the DMA block transfers.

The interrupt latch bit may be unmasked by the corresponding mask bit

in the same register. When initially enabling the mask bit, the correspond-

ing latch bit should be cleared first to clear out any request that may have

been inadvertently latched.

The interrupt service routine should test the buffer status or write to check

when the buffer is empty or full, in order to determine when it should

return from interrupt. This reduces the number of interrupts the ISR

must service.

For core interrupts programs need to perform two writes to the transmit

buffer to fill it. For the receiver, programs need to perform two reads from

the receive buffer to empty it. Then the next interrupt occurs when the

buffer becomes not full or not empty again. Two reads and or writes are

performed because the link port FIFO depth is two.

Service Request Interrupts

Link port service requests let a disabled (unassigned or assigned with buf-

fer disabled) link port cause an interrupt when an external access is

attempted. The transmit (

or receive data through a particular link port. Two processors can commu-

nicate without prior knowledge of the transfer direction, link port

number, or exactly when the transfer is to occur. The

described in regs appendix.

generated in a disabled (unassigned or assigned with buffer disabled) link

port. Each LSR is gated by mask bits before being latched in the

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) and receive (

is asserted externally, a link service request (LSR) is

ADSP-214xx SHARC Processor Hardware Reference

) request status bits of

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