Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 891

Table A-33. LCTLx Register Bit Descriptions (RW) (Cont'd)
Bit Name
9 LRRQ_MSK Link Port Receive Request Mask.
10 DMACH_
IRPT_MSK
11 LPIT_MASK Invalid Transmit Interrupt Mask.
12 EXTTXFR_
DONE_
MSK
31–13 Reserved
Status Registers (LSTATx)
Figure A-29 and
15
LPBS
Link Port Bus Status (Tx)
LERR
Link Buffer Rx Pack Error Status
FFST (6–5)
Link Buffer Status
EXTTXFR_DONE
External Transfer Done
Interrupt
Figure A-29. LSTATx Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Description
0 = Mask
1 = Unmask
DMA Channel Count Interrupt Mask. Must be set to generate inter-
rupt if DMA count is zero and is compatible with traditional SHARC
processors.
0 = Mask
1 = Unmask
0 = Mask
1 = Unmask
External Transfer Done Interrupt Mask. Valid for core and DMA
accesses. If set interrupt is generated when the FIFO is empty. Note if
bit 10 is also set for DMA, two interrupts are generated, one for
DMA count=0 and one for FIFO empty.
0 = Mask
1 = Unmask
Table A-34 describe the bit fields within this register.
14 13 12 11 10 9 8 7
Registers Reference
6 5 4 3 2 1 0
LTRQ
Link Port Tx Request Status
LRRQ
Link Port Rx Request Status
DMACH_IRPT
DMA Channel Interrupt
LPIT
Link Port Invalid Tx
Interrupt
A-65