Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 586

S/PDIF Receiver
Channel Status
The channel status for the first bytes 4–0 (consumer mode) are collected
into memory-mapped registers (
All other channel status bytes 23–5 (professional mode) must be manually
extracted from the receiver data stream.

Only the first 5 channel status bytes (40-bit) for consumer mode of
a frame are stored into the S/PDIF receiver status registers.
Operating Modes
This section describes the receiver channel status for the different modes.
Compressed or Non-linear Audio Data
The S/PDIF receiver processes compressed as well as non-linear audio data
according to the supported standards. The following sections describe how
this peripheral handles different data.
The AES3/SPDIF receiver is required to detect compressed or non-linear
audio data according to the AES3, IEC60958, and IEC61937 standards.
Bit 1 of byte 0 in the
linear PCM, (bit 1=0), or non-PCM audio, (bit 1=1). If the channel status
indicates non-PCM audio, the
used to generate an interrupt.) The
register) when set (=1) may indicate non-linear audio data as well. When-
ever this bit is set, the
MPEG-2, AC-3, DTS, and AAC compressed data may be transmitted
without setting either the
data, the IEC61937 and SPMTE 337M standards dictate that there be a
96-bit sync code in the 16-, 20- or 24-bit audio data stream. This sync
code consists of four words of zeros followed by a word consisting of
0xF872 and another word consisting of 0x4E1F. When this sync code is
13-16
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and
DIRCTL
register indicates whether the audio data is
DIRSTAT
DIR_NOAUDIO
DIR_VALID
bit flag is set in the
VALIDITY
bit or bit 1 of byte 0. To detect this
DIR_VALID
ADSP-214xx SHARC Processor Hardware Reference
/
DIRCHANA DIRCHANB
bit flag is set. (This bit can be
bit (bit 3 in the
DIR_RX_STAT
registers).
DIRSTAT
register.