Data Mask; Resetting The Controller; Operating Modes; Parallel Connection Of Sdrams - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

Data Mask

The SDRAM controller provides one

pins could be connected to

reset deassertion until SDRAM initialization completes, after that it's

driven low irrespective of whether any accesses occur.

Note that some manufacturer's require keeping

power-up initialization sequence.

Like any other peripheral, the SDRAM controller can be reset by a hard or

a soft reset. A hard reset puts the PLL in bypass mode where the SDRAM

clock runs at a lower frequency.

A soft reset also causes data loss, and programs need to re-initialize

SDRAM before it can be used again.

Running reset (

SDRAM controller.

The following sections provide on the operating modes of the SDRAM

To specify a SDRAM system, multiple possibilities are given based on the

different memory sizes. For a 16-bit I/O capability, the following can

• 2 x 16-bit/page 512 words

• 4 x 8-bit/page 1k words

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pin as an input) does not reset the

ADSP-214xx SHARC Processor Hardware Reference

), all SDRAM

pin is driven high from

high during the

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