Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 118

Operating Modes
Table 2-28. DMA Channel 0–66 Priorities (Cont'd)
DMA Peripheral
Channel Group
Number
55 J
56
57 K
58
59 L
60
61
62
2-40
www.BDTIC.com/ADI
Control/Status Parameter
Registers Registers
UART0RXCTL, IIUART0RX,
UART0RXSTAT IMUART0RX,
CUART0RX,
CPUART0RX,
UART0TXCTL, IIUART0TX,
UART0TXSTAT IMUART0TX,
CUART0TX,
CPUART0TX,
LCTL0, IILB0, IMLB0,
LSTAT0 ICLB0, CPLB0
LCTL1, IILB1, IMLB1,
LSTAT1 ICLB1, CPLB1
SPCTL7, IISP7A, IMSP7A,
SPMCTL7 CSP7A, CPSP7A
IISP7B, IMSP7B,
CSP7B, CPSP7B
SPCTL6, IISP6A, IMSP6A,
SPMCTL6 CSP6A, CPSP6A
IISP6B, IMSP6B,
CSP6B, CPSP6B
ADSP-214xx SHARC Processor Hardware Reference
Data Buffer Description
UARTRBR0 Buf- UART0 Receive
fer Buffer Register
UARTTHR0 UART0 Transmit
Buffer Holding Register
TXLB0 Link Port 0 Data
or (ADSP-2146x
RXLB0 only)
TXLB0 Link Port 1 Data
or (ADSP-2146x
RXLB0 only)
RXSP7A Serial Port 7A Data
or
TXSP7A
RXSP7B Serial Port 7B Data
or
TXSP7B
RXSP6A Serial Port 6A Data
or
TXSP6A
RXSP6B Serial Port 6B Data
or
TXSP6B