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start bit, which replaces the parity bit in the serial I
reception of the Z preamble and the start of a new block of channel status
and data bits.
Clock Recovery
The phased-locked loop for the AES3/SPDIF receiver is intended to
recover the clock that generated the AES3/SPDIF biphase encoded
stream. This clock is used by the receiver to clock in the biphase encoded
data stream and also to provide clocks for either the SPORTs, sample rate
converter, or the AES3/SPDIF transmitter. The recovered clock may also
be used externally to the chip for clocking D/A and A/D converters.
In order to maintain performance, jitter on the clock is sourced to several
peripherals. Jitter on the recovered clock must be less than 200 ps and, if
possible, less than 100 ps across all the sampling frequencies ranging from
27.2 kHz to 220.8 kHz (32 kHz – 15% and 192 kHz + 15%). Further-
more, once the PLL achieves lock, it is able to vary ±15% in frequency
over time. This allows for applications that do not use PLL unlocking.
To be AES11 compliant, the recovered left/right clock must be aligned
with the preambles within a + or – 5% of the frame period. Since the PLL
generates a clock 512 times the frame rate clock (512 ×
can be used and divided down to create the phase aligned jitter-free
left/right clock. For more information on recovered clocks, see
Recovery" on page
Output Data Format
The extracted 24-bit audio data, V, U, C and block start bits are sent on
the
pin in 32-bit I
DIR_DAT_O
frame sync is transmitted on the
ted on the
DIR_CLK_O
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
13-15.
2
S format as shown in
DIR_FS_O
pin. All three pins are routed through the SRU.
Sony/Philips Digital Interface
2
S stream, indicates the
FSCLK
Figure
pin and serial clock is transmit-
), this clock
"Clock
13-3. The
13-15
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