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Operating Modes
Set the clock divisor and source and low-phase word first, followed by the
control register enable bits, which must be set together. When the
register is set to zero (default) the FS pulse width is (divisor ÷ 2) for even
divisors and (divisor – 1) ÷ 2 for odd divisors. Alternatively, the
register could be set high for exactly one-half the period of
a 50% duty cycle, provided the FS divisor is an even number.
Clock Configuration Examples
For a
= 33.330 MHz the two PCGs provide the three synchronous
CLKIN
clocks
PCGx_CLK
sors are stored in 20-bit fields in the
The integer divisors for several possible sample rates based on 33.330
MHz
are shown in
CLKIN
Table 14-4. Precision Clock Generator Division Ratios
(33.330 CLKIN)
Sample Rate kHz)
130.195
65.098
43.398
32.549
26.039
21.699
18.599
1 The frame sync divisor should be an even integer in order to produce a 50% duty cycle
waveform. See
"Frame Sync" on page
14-18
www.BDTIC.com/ADI
,
and
for the SRCs and external DAC. These divi-
SCLK
FS
Table
14-4.
CLKDIV B
1
2
3
4
5
6
7
14-7.
ADSP-214xx SHARC Processor Hardware Reference
registers.
PCG_CTL
PCG Divisors
CLKDIV A
4
256
8
512
12
768
16
1024
20
1280
24
1536
28
1792
PCG_PW
PCG_PW
cycles for
CLKIN
1
FSDIV A
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