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17 SHIFT REGISTER –
ADSP-2147X
ADSP-2147x processors incorporate an 18 stage serial in, serial/parallel
out Shift Register (SR). The serial in–serial out mode can be used to delay
the serial data by a fixed amount of time. The serial output can also be
used to cascade the shift register modules on two or more processors. The
serial in–parallel out mode can be used to convert the serial data to paral-
lel.
Table 17-1
Table 17-1. Shift Register Specifications
Feature
Connectivity
Multiplexed Pinout
SRU DAI Required
SRU DAI Default Routing
SRU2 DPI Required
SRU2 DPI Default Routing
Interrupt Control
Protocol
Master Capable
Slave Capable
Transmission Simplex
Transmission Half Duplex
Transmission Full Duplex
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
lists the shift register specifications.
Availability
No
Yes
Yes
No
No
N/A
N/A
N/A
N/A
N/A
N/A
17-1
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