Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 732

Table of Contents

When initiating the transmission of a string, no special handling of the

first character is required. Set the

rupt service routine (ISR) load the first character from memory and write

bit should be cleared if the string transmission has completed.

Alternatively, UART writes and reads can be accomplished by ISRs. Sepa-

rate interrupt lines are provided for the transmit, receive, and error

signals. The independent interrupts can be enabled individually by the

For legacy reasons, the UART interrupt identification register (

still reflects the UART interrupt status (see

may require bundling all UART interrupt sources to a single interrupt

channel and servicing them all by the same software routine. This can be

established by globally assigning all UART interrupts to the same inter-

rupt priority using the programmable interrupt priority control registers.

Please note the special role of the

the service routine does not want to transmit further data. If software

stops transmission, it must read the

request. As long as the

that another interrupt of higher priority is pending), the

latch cannot be cleared by reading the

The following restrictions should be noted.

1. If either the line status interrupt or the receive data interrupt has

been assigned a lower interrupt priority by the interrupt controller,

a deadlock condition can occur. To avoid this, always assign the

lowest priority of the enabled UART interrupts to the

empty event.

2. Because of the destructive nature of reading the

shadow register (

the corresponding main register.

www.BDTIC.com/ADI

) is provided for reading the contents of

ADSP-214xx SHARC Processor Hardware Reference

bit (bit 1) and let the inter-

20-4). Legacy operation

Chapters

Table of Contents