Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 109

IOD1 BUS
EXTERNAL
PORT ARBITER
IOD1
EXTERNAL PORT
DMA BUS
DDR2
AMI or
SDRAM
Figure 2-2. I/O Processor Bus Structure

The IOD0 and IOD1 buses operate independently. However, in
some cases there may be address conflicts if both buses access the
same internal memory block. In this case, the IOD0 bus has first
priority.
Each I/O port has one or more DMA channels, and each channel has a
single request and a single grant. When a particular channel needs to read
or write data to internal memory, the channel asserts an internal DMA
request. The I/O processor prioritizes the request with all other valid
DMA requests. When a channel becomes the highest priority requester,
the I/O processor asserts the channel's internal DMA grant. In the next
clock cycle, the DMA transfer starts.
paths for internal DMA requests within the I/O processor.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
INTERNAL
MEMORY I/F
ARBITER
I/O SPEP
BUS
SPORT EP
(SPEP) ARBITER
CORE BUS
SPORTx
IOD0 BUS
PERIPHERAL
ARBITER
IOD0
PERIPHERAL DMA BUS
SPI UART
...
Table 2-28 on page 2-36
I/O Processor
LINK
HW
PORT ACC
shows the
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