Dma Transfers; Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Interrupts

DMA Transfers

Each link port supports a DMA channel.

Note that the link ports do not support internal to internal mem-
ory transfers like previous SHARCs (no link assignment register).
If internal to internal memory transfers are required, refer to
"External Port DMA" on page
In standard DMA operations, the software needs to set up the DMA
parameter registers before the link port control register is configured.
After setting the DMA enable bit the transfer starts until the word count
reaches zero, the DMA has finished.
Interrupts
The following sections and
interrupts.
Table 4-2. Link Port Interrupt Overview
Interrupt Interrupt Condition
Source
Link port –DMA RX/TX done
Core –core RX buffer full
DMA –core TX buffer empty
–link service request
–invalid transmit
attempt
4-16
www.BDTIC.com/ADI
3-65.
Table 4-2 provide details on using link port
Interrupt
Completion
–internal transfer
completion
–access completion
ADSP-214xx SHARC Processor Hardware Reference
Interrupt Default IVT
Acknowledge
RTI instruction Need to route
LPxI (PICRx) to
any PxxI