Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 119

Table 2-28. DMA Channel 0–66 Priorities (Cont'd)
DMA Peripheral
Channel Group
Number
63 M
64 N
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Control/Status Parameter
Registers Registers
PMCTL1, IIFIR, IMFIR,
FIRCTL1, ICFIR, IBFIR,
FIRCTL2, CIFIR, CMFIR,
FIRMACSTAT, CLFIR, CPFIR
FIRDMASTAT
PMCTL1, IIIIR, IMIIR,
IIRCTL1, ICIIR, IBIIR,
IIRCTL2, CIIIR, CMIIR,
IIRMACSTAT, CLIIR, CPIIR
IIRDMASTAT
PMCTL1 IIFFT, IMFFT,
FFTCTL1, ICFFT, IBFFT,
FFTCTL2, CIFFT, CMFFT,
FFTMACSTAT, CLFFT, CPIFFT,
FFTDMASTAT
PMCTL1, OIFIR, OMFIR,
FIRCTL1, OCFIR, OBFIR,
FIRCTL2, COFIR, CMFIR,
FIRMACSTAT, CLFIR, CPFIR
FIRDMASTAT
PMCTL1, IIIIR, IMIIR,
IIRCTL1, ICIIR, IBIIR,
IIRCTL2, CIIIR, CMIIR,
IIRMACSTAT, CLIIR, CPIIR
IIRDMASTAT
PMCTL1, OIFFT, OMFFT,
FFTCTL1, OCFFT, OBFFT,
FFTCTL2, COFFT, CMFFT,
FFTMACSTAT, CLFFT, CPOFFT,
FFTDMASTAT
I/O Processor
Data Buffer Description
Accelerator Input FIR, IIR, FFT
Buffers and FIFO Accelerator Input
Data
Accelerator Out- FIR, IIR, FFT
put Buffers and Accelerator Out-
FIFO put Data
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