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Processor Reset
Table 23-1. Reset Function Overview (Cont'd)
Reset Function
Core
1
Internal Memory
Peripherals
Booting
Power Management
2
Emulation Unit
1 Internal memory array does not have reset. Only power up/down can change array contents, (or
direct read/write by the core or DMA). However, if data exists in shadow FIFOs then that data
is reset with any of the above resets. The logic outside the memory array is reset by all of the above
three reset types, only the memory array contents remain unchanged.
2 There is an independent reset (
related logic is reset by the three resets types (HW Reset, SW Reset, Running Reset). Further-
more, no other part of the emulator is affected by the reset types.
function, including BTC.
Software Reset
In addition to the hardware reset, there is also support for a software reset,
which is asserted by setting bit 0 of the
Running Reset
When running reset is asserted (
asserted) and recognized, note the following.
• The core-PLL is NOT reset, and continues to run.
• Internal memory SRAM contents remain unaltered.
23-4
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Hardware Reset
Software Reset
Yes
No
Yes
Yes
Yes
No
) for the emulation interface. Enhanced Emulation (BTC)
TRST
RESETOUT
ADSP-214xx SHARC Processor Hardware Reference
Running Reset
Yes
Yes
No
No
Yes
Yes (except
SDRAM/DDR2)
Yes
No
No
No
No
No
resets the whole emulator
TRST
register.
SYSCTL
pin acting as an input and
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