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ADSP-2147x, ADSP-2148x External Port Registers
Table A-28. SDCTL Register Bit Descriptions (RW) (Cont'd)
Bit
Name
13–12
SDCAW
14
SDPSS
(WO)
15
SDSRF
(WO)
16
X16DE
18–17
SDTWR
19
SDORF
20
FAR
(WO)
21
FPC
(WO)
A-54
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Description
SDRAM Bank Column Address Width. SDRAM Page Size.
00 = 8 bits
01 = 9 bits
10 = 10 bits
11 = 11 bits
SDRAM Power-Up Sequence Start. The power-up sequence is trig-
gered by setting this bit. Note that there is a latency for this first
access to SDRAM because the SDRAM power-up sequence takes
many cycles to complete.
0 = No effect
1 = Enable power-up on next SDRAM access
Self-Refresh Enable. When the SDSRF bit is set to 1, self-refresh
entry command is triggered. Once the SDC completes any active
transfers, the SDC executes the sequence of commands to put the
SDRAM into self-refresh mode. Any access to the enabled SDRAM
bank causes the SDC to trigger a self-refresh exit command.
SDRAM External Data Path Width. This bit should always be set.
tWR Specification. Write To Precharge Delay) is 1–3 SDCLK cycles.
Based on the system clock frequency and the timing specifications of
the SDRAM used. Programmed parameters apply to all four banks in
the external memory.
Refer to the SDRAM data sheet.
Optional Auto-Refresh Command.
0 = Auto-refresh occurs when refresh counter expires
1 = Auto-refresh not performed
Force Auto-Refresh Command. Performs an auto-refresh immedi-
ately.
0 = No effect
1 = Force auto-refresh
Force Precharge. Performs a precharge all immediately.
0 = No effect
1 = Force precharge
ADSP-214xx SHARC Processor Hardware Reference
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