Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 958

DAI Signal Routing Unit Registers
Table A-77. Group C Sources – Frame Sync (Cont'd)
Selection Code
11010 (0x1A)
11011 (0x1B)
11100 (0x1C)
11101 (0x1D)
11110 (0x1E)
11111 (0x1F)
Pin Signal Assignment Registers
(SRU_PINx, Group D)
Each physical pin (connected to a bonded pad) may be routed using the
pin signal assignment registers (see
the SRU to any of the inputs or outputs of the DAI peripherals, based on
the 7-bit values listed in
signals that control the pins in other ways.
31 30
DAI_PB04_I (27–21)
DAI Pin Buffer 4 Input
15
DAI_PB03_I (20–14)
DAI_PB02_I (13–7)
DAI Pin Buffer 2 Input
Figure A-70. SRU_PIN0 Register (RW)
A-132
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Source Signal
DIR_FS_O
Reserved
PCG_FSA_O
PCG_FSB_O
LOW
HIGH
Table A-78. The SRU also may be used to route
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
ADSP-214xx SHARC Processor Hardware Reference
Description (Source Selection)
SPDIF RX Frame Sync Output
Precision Frame Sync A Output
Precision Frame Sync B Output
Logic Level Low (0)
Logic Level High (1)
Figure A-70 through
21 20 19 18 17 16
6 5 4 3 2 1 0
Figure A-74) in
DAI_PB03_I (20–14) (con't)
DAI Pin Buffer 3 Input
DAI_PB01_I (6–0)
DAI Pin Buffer 1 Input