Output Control Unit; Output Enable; Output Polarity - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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therefore be programmed in increments of 2

MHz peripheral clock). The

maximum value they can contain is 0x3FF (= 1023) which corresponds to

a maximum programmed dead time of:

This equates to an

grammed to zero by writing 0 to the

Modulation Registers" on page

Output Control Unit

ually enable or disable each of the 4 PWM outputs.

If the associated bit of the

ing PWM output is disabled, regardless of the value of the corresponding

duty cycle register. This PWM output signal remains disabled as long as

the corresponding enable/disable bit of the

gle update mode, changes to this register only become effective at the start

of each PWM cycle. In double update mode, the

be updated at the mid-point of the PWM cycle.

After reset, all four enable bits of the

that all PWM outputs are enabled by default.

The polarity of the generated PWM signals is programmed using the

PWMPOLARITY3–0

patterns can be produced. The polarity values can be changed on the fly if

ADSP-214xx SHARC Processor Hardware Reference

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rate of 200 MHz. Note that dead time can be pro-

registers, so that either active high or active low PWM

Pulse Width Modulation

(or 10 ns for a 200

registers are 10-bit registers, and the

registers (see

"Pulse Width

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