Mode Selection - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table 10-6. SPCTLx Control Bit Comparison (Cont'd)
Bit Standard Serial
Mode
Status
26
27–28
29
30–31

Mode Selection

The serial port operating mode can be selected via the
registers.
SPMCTLx/y
1. The operating mode bit 11 (
between I
2. The operating mode bit 17 (
between I
3. For packed mode, bit 11 (
( ) in the
MCEA
( ) in the
MCEB
4. In multichannel mode, the bit 0 (
enables the A channels and the bit 23 (
enables the B channels.
5. The
OPMODE
bit (
LAFS
The register is unique in that the name and functionality of its bits
SPCTLx
changes depending on the operation mode selected. In each section that
follows, the bit names associated with the operating modes are described.
Table 10-7 provides values for each of the bits in the SPORT serial
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
2
I S and
Left-justified Mode
2
S, left-justified, and standard serial/multichannel mode.
2
S mode and left-justified mode.
OPMODE
register enables the A channels and bit 23
SPMCTLx
register enables the B channels.
SPMCTLx
bit 17 serves for standard serial mode as late frame sync
).
Packed Mode
DERR_B
DXS_B
DERR_A
DXS_A
) of the
OPMODE SPCTLx
) of the
OPMODE SPCTLx
) of the
SPCTLx
) in the
MCEA SPMCTLx
) in the
MCEB
Serial Ports
Multichannel Mode
and the
SPCTLx
register selects
register selects
register and bit 0
register
register
SPMCTLx
10-23