Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 569

ratio. Hard mute, soft mute, and auto mute only control the muting of
the input data to the SRC.
Table 12-4 provides an overview of SRC interrupts.
Table 12-4. SRC Interrupt Overview
Interrupt Source
DAI SRC
RX/TX (I2S, left/right
justified, TDM, 4
channels)
Debug Features
The asynchronous sample rate converter allow the bypass mode. When the
bit is set (=1), the input data bypasses the sample rate converter
BYPASS
and is sent directly to the serial output port. This mode can be used for
testing both ports when the input and output sample rates are at the same
frequency, therefore both in- and output ports can be routed to the same
serial clock and frame sync.
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Asynchronous Sample Rate Converter
Interrupt Condition
– Mute out asserted
(SRC init, SRC sample
rate change)
Interrupt Interrupt
Completion Acknowledge
Read-to-clear
DAI_IRPTL_x
+ RTI instruction
Default IVT
P0I, P12I
12-17