Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 903

Table A-43. FFTCTL2 Register Bit Descriptions (RW)
Bits Name
0 FFT_RPT
1 FFT_CPACKIN
2 FFT_CPACKOUT
6–3 FFT_LOG2VDIM
11–7 VDIM
15–12 FFT_LOG2HDIM
20–16 HDIM
28–21 NOVER256
31–29 Reserved
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Description
Accelerator Repeat. If this bit is set and the program needs to
change the parameters of the FFT (such as length), first clear
the FFT_EN and FFT_START bits in the FFTCTL1. Next
change the FFT parameters as needed. Then set FFT_EN
and, finally, set FFT_START. The accelerator is in READ-
ING mode and is ready to read in data/twiddles and compute
FFT with the newly programmed parameters.
0 = Go to idle when done
1 = Repeat when done
Complex Word Input Packing for <512 Words.
0 = No packing, first all reals, then all imag are received by
the accelerator
1 = Complex numbers are packed Real/Imag. For >256
words, this bit is always set.
Complex Word Output Packing for <512 Words.
0 = No packing, first all reals, then all imag are sent by the
accelerator
1 = Complex numbers are packed Real/Imag. For >256
words, this bit is always set.
Log2 (VDIM).
VDIM/16.
Vertical Column Dimension of the FFT computation matrix
V = 16, VDIM = 1
V = 32, VDIM = 2
V = 64, VDIM = 3
V = 128, VDIM = 4
V = 256, VDIM = 5
Log2 (HDIM).
HDIM/16. Horizontal Column Dimension of the FFT com-
putation matrix. For small FFTs, (<512 points) only VDIM
required HDIM = 0.
×
N/256 = HDIM VDIM (used for large FFTs)
Registers Reference
A-77