Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 314

FFT Accelerator
Peripheral Interrupt
connect FFT interrupts to the peripheral interrupt inputs of the core.
Table 6-2 povides an overview of FFT interrupts.
Table 6-2. FFT Interrupt Overview
Interrupt Interrupt Condition
Sources
FFT - Input DMA done
(2 channels) - Output DMA done
- MAC Status (NaN,
Denormal, Underflow,
overflow)
Interrupt Sources
One interrupt is shared by all the DMA interrupts and the other by MAC
status interrupts. Separate status registers are provided to further differen-
tiate the various sources.
Servicing DMA Interrupts
The DMA interrupt is shared by the input DMA and the output DMA.
The interrupts are generated at the end of every chain or at the end of an
entire DMA sequence, depending on the
pointer registers. When a DMA interrupt occurs, programs can find
whether the input DMA interrupt occurred or the output DMA interrupt
occurred by reading the DMA status register (
interrupt status bits are sticky and are cleared when the DMA status regis-
ter is read.
Servicing MAC Status Interrupts
A MAC status interrupt is generated whenever a floating-point operation
results in an underflow or an overflow condition or when the operands of
a floating-point operand is a denormal number or NAN. When a MAC
6-18
www.BDTIC.com/ADI
Control). Source bits
Interrupt
Completion
Internal transfer
completion
ADSP-214xx SHARC Processor Hardware Reference
and are used to
ACC0I ACC1I
Interrupt
Acknowledge
RTI instruction
value in the respective chain
PCI
). The DMA
FFT_DMASTAT
Default IVT
Need to route
ACCxI
(PICRx) to
any PxxI