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Servicing Interrupts for DMA
The following steps describe how to handle an IDP ISR for DMA.
1. An interrupt is generated and program control jumps to the ISR
when the DMA for a channel completes.
2. The program clears the
a. To ensure that the DMA of a particular IDP channel is
complete, (all data is transferred into internal memory) wait
until the
the
DMA (for example a SPORT DMA) is occurring at the
same time as the IDP DMA.
b. As each DMA channel completes, a corresponding bit in
either the
DMA channel is set (
3. The program clears (= 0) the channel's
IDP_CTL1
4. Reprogram the DMA registers for finished DMA channels.
More than one DMA channel may have completed during this
time period. For each, a bit is latched in the
DAI_IMASK_H
grammed. If any of the channels are not used, then its clock and
frame sync should be held
5. Read the
rupts have been generated.
• If the value(s) are not zero, repeat step 4.
• If the value(s) are zero, continue to step 6.
ADSP-214xx SHARC Processor Hardware Reference
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IDP_DMA_EN
IDP_DMAx_STAT
register. This is required if a high priority
DAI_STAT
DAI_IMASK_L
register which has finished.
registers. Ensure that the DMA registers are repro-
LOW
or
DAI_IMASK_L
DAI_IMASK_H
bit in the
IDP_CTL
bit of that channel becomes zero in
or
register for each
DAI_IMASK_H
).
IDP_DMAx_INT
IDP_DMA_ENx
DAI_IMASK_L
.
registers to see if more inter-
Input Data Port
register.
bit in the
or
11-31
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