Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 84

DMA Channel Registers
Table 2-3. Modify Registers (Cont'd)
Register Name
IMIIR
CMIIR
OMIIR
IMFFT
OMFFT
IMMTMW
IMMTMR
IMEP0–1
EMEP0–1
Count registers. These registers, shown in
of words remaining to be transferred to or from memory on the corre-
sponding DMA channel.
Table 2-4. Count Registers
Register Name
ICSP0–7A
ICSP0–7B
ICSPI
ICSPIB
IDP_DMA_C0–7
ICLB0–1
CUART0RX
CUART0TX
ICFIR
CCFIR
OCFIR
2-6
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Width (Bits) Description
16 Accelerator IIR data input
16 Accelerator IIR coeff input
16 Accelerator IIR output
16 Accelerator FFT input
16 Accelerator FFT output
16 MTM Write
16 MTM Read
16 External Port
27 External Port (external)
Width (Bits) Description
16 SPORTA
16 SPORTB
16 SPI
16 SPIB
16 IDP
16 Link Port
16 UART0 Receiver
16 UART0 Transmitter
16 Accelerator FIR data input
16 Accelerator FIR coeff input
16 Accelerator FIR output
ADSP-214xx SHARC Processor Hardware Reference
Table 2-4, indicate the number