Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 831

PWMONDPIEN
DPI Pins as PWM Signals
PWM3EN
Pulse Width Modulation Select
PWM2EN
Pulse Width Modulation Select
PWM1EN
Pulse Width Modulation Select
PWM0EN
Pulse Width Modulation Select
EPDATA (23–21)
Data Pin Mode Select
Figure A-1. SYSCTL Register
Table A-2. SYSCTL Register Bit Descriptions
Bit Name
15–0 The bits are used for controlling core function. Refer to the SHARC Processor Program-
ming Reference.
16 IRQ0EN
17 IRQ1EN
18 IRQ2EN
19 TMREXPEN
20 MSEN
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
31 30 29 28 27 26 25 24
Description
Flag0 Interrupt Mode.
0 = Flag0 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag0 pin is allocated to interrupt request
Flag1 Interrupt Mode.
0 = Flag1 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag1 pin is allocated to interrupt request
Flag2 Interrupt Mode.
0 = Flag2 pin is a genera-purpose I/O pin. Permits core writes.
1 = Flag2 pin is allocated to interrupt request
Flag Timer Expired Mode.
0 = Flag3 pin is a general-purpose I/O pin. Permits core writes.
1 = Flag3 pin output is timer expired signal (TMREXP).
Memory Select Enable. Selects between FLGx/
TMREXP. Together with bits 19–18 generate a truth table. Detailed
modes of programming for these bits are given in
Multiplexing" on page
0 = FLAG/
IRQx
1 = Enables FLAG2 and 3 (
Registers Reference
23 22 21 20 19 18 17 16
23-28.
pins are selected
and TIMEXP) as
IRQ2
IRQ0EN
Flag0 Mode
IRQ1EN
Flag1 Mode
IRQ2EN
Flag2 Mode
TMREXPEN
Flag3 Mode
MSEN
Memory Select Enable
.
IRQ0
.
IRQ1
.
IRQ2
/ or
AMI_MSx IRQx
"Core FLAG Pins
and 3
MS2
A-5