Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 562

Operating Modes
LRCLK
SCLK
MSB
SDATA
LRCLK
SCLK
MSB
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
MSB
SDATA
NOTES
1
LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (f
2
SCLK FREQUENCY IS NORMALLY 64
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN.
3
PLEASE NOTE THAT 8 BITS OF EACH 32-BIT SUBFRAME ARE USED FOR TRANSMITTING
MATCHED-PHASE MODE DATA.
Figure 12-3. SRC Data Format
TDM Daisy Chain Mode
The SRCs are daisy chained together to achieve the TDM mode of
operation.
12-10
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LEFT CHANNEL
LSB
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LSB
I2S MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
MSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LSB
TDM MODE – 16 BITS TO 24 BITS PER CHANNEL
LRCLK EXCEPT FOR TDM MODE WHICH IS N
ADSP-214xx SHARC Processor Hardware Reference
RIGHT CHANNEL
MSB
RIGHT CHANNEL
MSB
LSB MSB
MSB
s
1/f
).
S
64 f ,
S
LSB
LSB
RIGHT CHANNEL
LSB
LSB