Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 770

Phase-Locked Loop (PLL)
If the bit is set, new post divider ratios are picked up on the fly and
DIVEN
the clocks smoothly transition to their new values within 14 core clock
( ) cycles.
CCLK

Post divider ratio changes (
The output clock generator block also controls bypass mode. For a
description of the
isters" on page A-6
Registers" on page
Core Clock (CCLK)
The bits define the VCO output clock to core clock ratio to build the
PLLD
processor core clock (
new division ratios are implemented on the fly.
IOP Clock (PCLK)
The peripheral clock is derived from the core clock with a fixed post divi-
sor of 2. This clock is the master clock for all peripherals (except SDRAM)
including the I/O processor (IOP).
SDRAM/DDR2 Clock (SDCLKx/DDR2_CLK)
The DDR2/ SDRAM clock is derived from the core clock. The default
divisor is 2. After
are driven with
troller configuration. Note that the
whenever there is a change from the default ratio.
Default PLL Hardware Settings
Table 22-2 demonstrates the internal core clock switching frequency
across a range of
any given frequency may be constrained by the operating range of the
22-6
www.BDTIC.com/ADI
PLLD
bits, see "ADSP-2146x Power Management Reg-
PMCTL
and "ADSP-2147x/ADSP-2148x Power Management
A-12.
). The post divider can be changed any time and
CCLK
is deasserted, both DDR2/SDRAM output clocks
RESET
/2 = , independent of the DDR2/SDRAM con-
CCLK PCLK
frequencies. The minimum operational range for
CLKIN
ADSP-214xx SHARC Processor Hardware Reference
bits) do not require bypass mode.
bit needs to be changed
DIVEN